Hello Pelle!
I almost write my own ARM dissassembler and find out that your ARM assembler doesn't support all types of MSR instructions. I use your IDE for making test programs.
For example try to compile "MSR CPSR_c, R0" code. It's usuall code for reading processor mode.
Your assembler "eat" only CPSR, CPSR_ALL, SPSR, SPSR_ALL, CPSR_FLG, SPSR_FLG fields. But there are a lot of cases: CPSR_fc, CPSR_c, CPSR_f and etc. The same situation with SPSR.
Can you correct this? It will be great!
Thanks
PS. mask in MSR instruction for CPSR (SPSR the same), bits[19:16]:
0b0000 - UNPREDICTABLE
0b0001 - CPSR_c = CPSR_ctl
0b0010 - CPSR_x
0b0011 - CPSR_xc
0b0100 - CPSR_s
0b0101 - CPSR_sc
0b0110 - CPSR_sx
0b0111 - CPSR_sxc
0b1000 - CPSR_f = CPSR_flg
0b1001 - CPSR_fc = CPSR = CPSR_all
0b1010 - CPSR_fx
0b1011 - CPSR_fxc
0b1100 - CPSR_fs
0b1101 - CPSR_fsc
0b1110 - CPSR_fsx
0b1111 - CPSR_fsxc
