Code Density Comparison of two unsigned 24-bit values: x64 vs ϕEngine

[PabloMack]

I just rewrote an assembly function for the Pelles C assembler that compares two unsigned 24-bit integers. The function returns 1 for greater, 0 for equal and -1 for less than. I thought some of you might find it interesting. The x64 version was 45 bytes in size. I wrote a ϕEngine version and it is 15 bytes, only 1/3 the size. But this should not be surprising since ϕEngine can process 3-byte integers natively. Here is the source code:

 ⅅCPU Eng32
ut_cmp‡: ⅅPBeg
    ld     ⓊQ0,ut:(Ⓡ0)
    cmp    ⓊQ0,ut:(Ⓡ1)
    s.A*   Ⓒ0,ⓊQ0
    s.B*   Ⓒ0,ⓈQ0
    rts
 ⅅPEnd

Notice that the processing has to be done in a 32-bit register (ⓊQ0) which also is used to hold the return value. The two source values are extended during the loads so there are no separate conversion routines. The second load is part of the compare instruction. Most of the code is for producing a return value from the flags that are set by the compare. Since this operation can be done inline cheaper than even just the setup for a function call, the function would actually never be needed in ϕPPL or ϕAsm.

[John Z]

So - what actual hardware or hardware emulator is running your ϕEngine?
Using ARM?, QEMU,  custom FPGA?

John Z

[PabloMack]

So - what actual hardware or hardware emulator is running your ϕEngine?
Using ARM?, QEMU,  custom FPGA?

John Z

I am writing a simulator I call ϕSim that runs on Windows. It's main purpose is to prove out the logic of how it works. I have been using OpenWatcom for writing the SW tool chain but it only runs on 32-bit x86. That's why I have been evaluating PellesC for 64-bit execution. I am also evaluating TileLink for writing a soft core to run as a standalone SOC. Of course I will have to prove it out on an FPGA. So far I am impressed with TL as it is open source and has growing support. It is the primary environment for RISC-V. But TL is not married to RISC-V and I think it could serve ϕEngine quite well.

ϕEngine's instruction set was developed and is maintained by a program I started writing in 2018. It generates C source code for the assembler (ϕAsm) as well as for ϕSim. I plan to generate Verilog source code to define the soft core and SOC. This is the natural place to do it since it has direct access to the data structures that define ϕEngine's instruction set.