Ahhh! Thank you for the correction. I am getting true on two out of three ...
The output is:
atomic_is_lock_free(void*):true
atomic_is_lock_free(uintptr_t):true
atomic_is_lock_free(structure):false
On x86 the atom structure can be implemented with cmpxchg8b.
Still not sure why I am getting false for atomic_is_lock_free(&AtomStruct).
The atomic qualifier is supposed to assure that operations on the object are made atomically, substantially the whole object is modified or acquired integrally without contamination from concurrent accesses. This basically means that whatever object having correspondence with a processor atomic instruction is intrinsically atomic.
A structure is by default larger of CPU atomic instructions, then is intrinsically not free from lock. And this is the correct answer you get.
Anyway changing a member of the structure, that is one of the intrinsically atomic instructions of the CPU, will be executed in standard way. I.e. The following:
atomic_store(&AtomStruct.a, 1);Will be in X86-32bits:
mov eax,1
xchg dword ptr [AtomStruct],eax
I hope to have been clear.
Wrt to my DWCAS proxy collector, I need a pointer and an intptr_t to be at least lock-free.
struct ct_proxy_dwcas
{
struct ct_proxy_node* node;
intptr_t count;
};
We can do this in 32-bit systems with cmpxchg8b. We can do this in 64-bit systems with cmpxchg16b.
https://www.felixcloutier.com/x86/CMPXCHG8B:CMPXCHG16B.htmlWe can do this in IBM wrt the Principals of Operation for a lock-free stack and ABA counter:
http://publibfp.dhe.ibm.com/epubs/pdf/dz9zr009.pdfTake a look at Appendix A-50 Free Pool Manipulation.
Also, what about, 32-bit x86:
AC_SYS_APIEXPORT
int AC_CDECL
np_ac_i686_atomic_dwcas_fence
( void*,
void*,
const void* );
np_ac_i686_atomic_dwcas_fence PROC
push esi
push ebx
mov esi, [esp + 16]
mov eax, [esi]
mov edx, [esi + 4]
mov esi, [esp + 20]
mov ebx, [esi]
mov ecx, [esi + 4]
mov esi, [esp + 12]
lock cmpxchg8b qword ptr [esi]
jne np_ac_i686_atomic_dwcas_fence_fail
xor eax, eax
pop ebx
pop esi
ret
np_ac_i686_atomic_dwcas_fence_fail:
mov esi, [esp + 16]
mov [esi + 0], eax;
mov [esi + 4], edx;
mov eax, 1
pop ebx
pop esi
ret
np_ac_i686_atomic_dwcas_fence ENDP
Double Width Compare and Swap (DWCAS) should be on C11 and C++11 when the architecture supports it.
I know that C++11 totally supports lock-free DWCAS on architectures that provide it, works like a charm. Read:
https://groups.google.com/forum/#!original/lock-free/X3fuuXknQF0/Ho0H1iJgmrQJWhy is atomic_is_lock_free wrt a pointer to a double width structure giving me false, when it totally works lock-free on the architecture itself?
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