Author Topic: High Performance 64-bit CPU Design  (Read 2905 times)


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High Performance 64-bit CPU Design
« on: April 16, 2020, 02:20:37 PM »
I have a long-time interest in computer architectures (since about 1977 or so). I have lots of hands-on experience using the Zilog Z80, MOS 6502/6510, Motorola 68K/HC08/HC12 and Intel x86 as well as DEC PDP-11 and VAX-11 and,  most recently, ARM CortexM.

All of these architectures have strengths and weaknesses and it is interesting to compare these to one another. About the time of RISC's ascendancy, I was actively developing my ideas on how an ideal general-purpose processor should work. That was in about 1991 or so. I always told myself that one day I would take this ball and run with it. But the advanced features that this processor would have was too ambitious to be done in a 32-bit processor. It would really need a 64-bit address space.

So, finally I decided that it was time to make it happen. I have spent much of the last year designing a 64-bit CPU called ϕEngine. It is amazing how things are falling into place. I first wrote a program that manages the instruction set. That was done using the Watcom compiler. But that only runs in 32-bits. About a month ago I decided to write a simulator that will run in 64-bit Windows This is my first ambitious project to use the PellesC compiler and this runs in 64-bit Windows. It is going to be quite complicated but I will be very pleased to see it run machine code. I have already purchased a Xilinx FPGA to implement an emulator in actual hardware. I plan to design the hardware using Verilog. This processor has a very unique virtual memory system that will do really cool stuff that no other processor can do. A month ago I redesigned the instruction set and this processor has a lot of RISC-like features such as it is a load/store architecture. But it is not RISC because it has a variable instruction length like the AMD64. But it is very different from the AMD64 in many ways.

Here is a summary list of features:

1. Variable Instruction Length (from 1 to N bytes)
2. Assembler will be called ϕAsm.
3. 32 64-bit Integer Registers that can be used as:
  a. 64 32-bit Integer Registers
  b. 128 16-bit Integer Registers
  c. 256 8-bit Integer Registers
4. 32 Address Registers. This is similar to the Motorola 68K.
5. 32 Floating Point Registers (support for 128bit IEEE quad-precision)
6. All Source Code is Unicode-based (ϕAsm and ϕPPL)
7. Virtual memory architecture implements a powerful statically linked object-oriented methodology. No more need for DLL's.
8. Supports up to 256TBytes physical memory

To make full use of this processor, a new programming language is under development (since about 1988). This is called ϕPPL (ϕ Parallel Programming Language). I plan to write an operating system using ϕPPL to run on ϕEngine and that will be called ϕOS. It will be much more powerful than Windows or Linux. This is not an open-source project. I would welcome collaborators who are interested in building a consortium of members who think that their work is worth getting paid for. I have created a group on LinkedIn called "ϕSystem Architectural Group" where we can share ideas and plan strategies.
« Last Edit: April 17, 2020, 04:02:48 PM by PabloMack »